Single-core 32-bit RISC-V CPU, up to 240 MHz.Single-core 32-bit RISC-V CPU, up to 96 MHz.30 (QFN40) / 22 (QFN32) programmable GPIOs.IEEE 802.11ax (Wi-Fi 6) on 2.4 GHz, supporting 20 MHz bandwidth in 11ax mode, 20 or 40 MHz bandwidth in 11b/g/n mode.Low Power 32-bit RISC-V CPU, up to 20 MHz, implementing RV32IMAC.High performance 32-bit RISC-V CPU, up to 160 MHz, implementing RV32IMAC.Ultra-low power FSM coprocessor similar to previous ESP32 and ESP32-S2.Ultra-low power RISC-V (RV32IMC) coprocessor clocked at 17.5 MHz approximately.Capable of connecting to external PSRAM and Flash via Quad SPI or Octal SPI, and share the same 32 MiB address space.512 KiB SRAM, 384 KiB ROM, and 16 KiB RTC SRAM.Added instructions to accelerate machine learning applications.Dual-core Xtensa LX7 CPU, up to 240 MHz, and supporting single-precision FPU.400 KiB SRAM, 384 KiB ROM, and 8 KiB RTC SRAM.Single-core 32-bit RISC-V CPU, up to 160 MHz.320 KiB SRAM, 128 KiB ROM, and 16 KiB RTC SRAM.Single-core Xtensa LX7 CPU, up to 240 MHz.
Xtensa® single-/dual-core 32-bit LX6 microprocessor(s).Additionally, the original ESP32 was revised (see ESP32 ECO V3, for example). These chips have different CPUs and capabilities, but all share the same SDK and are largely code-compatible. They form the ESP32 family of microcontrollers. Since the release of the original ESP32, a number of variants have been introduced and announced. Wake up from GPIO interrupt, timer, ADC measurements, capacitive touch sensor interrupt.
#Nucleo board i2c peripheral generator#
#Nucleo board i2c peripheral full#
10 × touch sensors ( capacitive sensing GPIOs).Bluetooth: v4.2 BR/EDR and BLE (shares the radio with Wi-Fi).
CPU: Xtensa dual-core (or single-core) 32-bit LX6 microprocessor, operating at 160 or 240 MHz and performing at up to 600 DMIPS.Features of the ESP32 include the following:
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